Location

Bengaluru/ Pune/ Hyderabad/ Noida

Experience

3+ Years

Job Description

• Specification Interpretation: Collaborate with system architects to understand the high-level specifications and requirements for the digital design.
• RTL Design: Create RTL descriptions of digital circuits using hardware description languages (e.g., Verilog, SystemVerilog) to capture the desired functionality.
• Digital Logic Design: Implement digital logic functions, state machines, and control units to meet design goals for performance, power, and area (PPA).
• Synthesis Optimization: Work with synthesis tools (e.g., Synopsys Design Compiler, Cadence Genus) to optimize the RTL code for efficient gate-level implementation.
• Clock Domain Crossing (CDC) Analysis: Address clock domain crossing issues by synchronizing signals that cross different clock domains.
• Low-Power Design: Implement low-power design techniques, including clock gating, power gating, and voltage scaling, to reduce power consumption while maintaining functionality.
• Timing Analysis: Use static timing analysis (STA) tools to ensure that the design meets timing constraints and operates at the desired clock frequency.
• Simulation: Conduct functional simulation and RTL-level verification using simulation tools (e.g., ModelSim) to verify the correctness of the RTL code.
• Debugging: Identify and address issues in the RTL code and collaborate with cross-functional teams to resolve them.
• Documentation: Maintain comprehensive documentation of the RTL code, design constraints, and any design-specific considerations.
• IP Integration: Integrate digital IP blocks from internal or external sources into the overall design, ensuring compatibility and functionality.
• Collaboration: Collaborate closely with physical design, verification, and DFT (Design for Test) engineers to ensure successful integration of digital components into the complete IC design.