Std. Cell/ Layout Engineers

  • Location

    Bengaluru/ Pune/ Hyderabad/ Noida

  • Job Description

    • Good understanding of electronics basic concepts and applications
    • Good understanding of logic gates, flip flops, latches, multiplexers, level shifters, digital logics etc
    • Knowledge of CMOS processes and issues in deep submicron process technologies
    • CMOS design and layout design concepts (good understanding of lower node technologies is preferred)
    • Familiarity with ASIC design flow and layout automation
    • Prior knowledge of Standard cell is required in technologies like N7, N5, N3, SS4 etc
    • Knowledge of EDA tools for layout/schematic design is required
    • Programming languages C / Python / Perl / UNIX is mandatory (expertise will be added advantage)
    • Out of box and innovative thinking capability
    • Systematic approach to solve any problem
    • Excellent written and verbal communication skills to work with other teams
    • Should be able to adjust and work with people of all regions in the world
    • Should be able to work autonomously and handle projects unsupervised

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