Career

Career at Digicomm

Let's grow mutually & change the world ....

At Digicomm, Making work better for our customers starts with our core values. We constantly strive to achieve our mission of making our customers SHINE as guided by our core values of passion and integrity, sustainable value through innovation, and quality.

A continuous learning environment that provides ground for constant learning is the biggest reason that keeps our highly skilled engineers constantly motivated and rearing to go for higher challenges.

If these match the way you think, we would love to talk to you about joining our team! Apply for one of our open jobs.

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Available Vacancies

  • Qualifications

    BTECH/MTECH

  • Job Description

    • Expertise on Physical Design.
    • Expertise on complete PNR flow CTS,routing, Timing Closure.
    • Good expertise on timing constraints and timing closure methodologies.
    • Hands on Expertise on block level and top level.
    • IR drop/EM analysis experience is preferred.
  • Qualifications

    BTECH/MTECH

  • Job Description

    • Working experience with standard protocols such as USB, PCIe, Ethernet, MIPI, AMBA Bus, etc.
    • Must have experience with IP level and SoC level verification with test plan development, test bench coding.
    • Must have strong background in logic verification with very good debugging skill.
    • Experience in directed test and constrained randomized test development..
    • Must have experience in code coverage and functional coverage analysis.
  • Qualifications

    BTECH/MTECH

  • Job Description

    • Needs hands-on Experience on SerDes Blocks like Tx, RX, PLL.
    • Good understanding of Analog Layout basics.
    • Finfet Layout experience is an added advantage.
    • Need quick learning ability and good attitude.
  • Qualifications

    BTECH/MTECH

  • Job Description

    • Should have good post silicon DFT bringup and debug experience.
    • Hands on in multi-vendor DFT tools.
    • Create test plan for complex ASICs and drive the DFT implementation.
    • Ability to guide people, multiplex many issues and set priorities.
  • Qualifications

    BTECH/MTECH

  • Job Description

    • Experience in ECO flows.
    • Experience with liberty timing models and STA tools (e.g., Primetime, Tempus).
    • Experience with Static Timing Analyses, sign-off corner definitions, process margining.
    • Experience in Timing Debug, Timing Fixes for inter clock domain violations.
    • Constraint exceptions,OCV concepts,LEC..
  • Experience

    Experiencel 4+ for Bangalore, 3+ for Noida

  • Job Description

    This job involves implementation of physical designs independently for medium to complex hard macros with Innovus and ICC2 tools. This implementation will be targeted to lower node technologies and has various stages of block implementation such as floorplanning, placement, clock tree synthesis, routing and optimization. It also involves working on the signoff closure related fixes and runs such as timing and power analysis, formal verification and physical verification.

  • Experience

    3+ Years

  • Job Description

    • Hands on experience in high speed SERDES/ RF/ DDR IO/Analog layout design.
    • Must have worked on lower nodes, preferably 7nm and 5nm.
    • Must have good hands on experience in doing layout, starting from transistor level drawings to block level integration.
    • Knowhow of best practices followed in analog layouts.
    • Good knowledge in optimized layout design for better performance.
  • Experience

    2+ Years

  • Job Description

    • Should know how to run and fix DRC/LVS/Antenna/ERC fixing etc at full_chip level in caliber
    • Should have knowledge of creating scripts.
    • Must have worked on lower nodes, preferably 7nm and 5nm.
    • Should be able to set the PV flows and debug any flow related issues.
  • Experience

    3+ Years

  • Job Description

    • Mentor Tessent Testcompress : expert
    • Mentor LBIST Inserion and verification
    • Cadence NcSim ? timing and zero delay mainly DFT verification
    • Cadence genus, LEC : Intermediate
    • Spyglass DFT - Nice to have
    • IJTAG ? nice to have
  • Experience

    3+ years

  • Job Description

    • Needs hands-on Experience on SerDes Blocks like Tx, RX, PLL.
    • Experience in Logic design / RTL coding is a must.
    • Experience is SoC design and integration for complex SoCs is a must.
    • Experience in Verilog/System-Verilog is a must.
    • Experience in Multi Clock designs, Asynchronous interface is a must.
    • Experience in using the tools in ASIC development such as Lint and CDC.
    • Experience in Synthesis / Understanding of timing concepts is a plus.
    • Experience in ECO fixes and formal verification.
    • Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture.
    • Excellent oral and written communications skills.
    • Proactive, creative, curious, motivated to learn and contribute with good collaboration skills
  • Experience

    4+ years

  • Job Description

    • Experience in ECO flows.
    • Experience with liberty timing models and STA tools (e.g., Primetime, Tempus).
    • Experience with Static Timing Analyses, sign-off corner definitions, process margining, and setting up of frequency targets with technology scaling and PDK changes.
    • Experience in Timing Debug, Timing Fixes for inter clock domain violations, General Timing Analysis & Issues debug, MMMC mode Timing analysis, SDC interpretation, Constraint exceptions, OCV concepts, LEC.
  • Experience

    4+ years

  • Job Description

    • Working experience with standard protocols such as USB, PCIe, Ethernet, MIPI, AMBA Bus, etc.
    • Must have experience with IP level and SoC level verification with test plan development, test bench coding.
    • Must have strong background in logic verification with very good debugging skill.
    • Experience in directed test and constrained randomized test development.
    • Must have experience in code coverage and functional coverage analysis.
    • Expertise in C, Verilog, SystemVerilog, UVM/OVM.